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1a07b330f8
Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.
10 lines
178 B
Verilog
10 lines
178 B
Verilog
module top
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#(parameter X_WIDTH=6, Y_WIDTH=6, A_WIDTH=12)
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(
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input [X_WIDTH-1:0] x,
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input [Y_WIDTH-1:0] y,
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output [A_WIDTH-1:0] A,
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);
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assign A = x * y;
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endmodule
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