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https://github.com/YosysHQ/yosys
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119 lines
2.6 KiB
Text
119 lines
2.6 KiB
Text
read_verilog -icells -formal <<EOT
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module top(input CI, I0, output [1:0] CO, output O);
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wire A = 1'b0, B = 1'b0;
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\$__ICE40_CARRY_WRAPPER #(
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// A[0]: 1010 1010 1010 1010
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// A[1]: 1100 1100 1100 1100
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// A[2]: 1111 0000 1111 0000
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// A[3]: 1111 1111 0000 0000
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.LUT(~16'b 0110_1001_1001_0110),
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.I3_IS_CI(1'b1)
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) u0 (
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.A(A),
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.B(B),
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.CI(CI),
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.I0(I0),
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.I3(1'bx),
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.CO(CO[0]),
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.O(O)
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);
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SB_CARRY u1 (.I0(~A), .I1(~B), .CI(CI), .CO(CO[1]));
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endmodule
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EOT
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read_verilog -icells -lib +/ice40/abc9_model.v +/ice40/cells_sim.v
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equiv_opt -assert -map +/ice40/abc9_model.v -map +/ice40/cells_sim.v ice40_opt
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design -load postopt
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select -assert-count 1 t:*
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select -assert-count 1 t:$lut
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# https://github.com/YosysHQ/yosys/issues/1543
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design -reset
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read_verilog <<EOT
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module delay_element (input wire clk, input wire reset, input wire enable,
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input wire chainin, output wire chainout, output reg latch);
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reg const_zero = 0;
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reg const_one = 1;
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wire delay_tap;
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//carry logic
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(* keep *) SB_CARRY carry ( .CO(chainout), .I0(const_zero),
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.I1(const_one), .CI(chainin));
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//flip flop latch
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(* keep *) SB_DFFER flipflop( .Q(latch), .C(clk), .E(enable),
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.D(delay_tap), .R(reset));
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//LUT table
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// the LUT should just echo the carry in (I3)
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// carry I0 = LUT I1
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// carry I1 = LUT I2
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// carry in = LUT I3
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// LUT_INIT[0] = 0
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// LUT_INIT[1] = 0
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// LUT_INIT[2] = 0
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// LUT_INIT[3] = 0
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// LUT_INIT[4] = 0
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// LUT_INIT[5] = 0
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// LUT_INIT[6] = 0
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// LUT_INIT[7] = 0
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// LUT_INIT[8] = 1
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// LUT_INIT[9] = 1
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// LUT_INIT[10] = 1
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// LUT_INIT[11] = 1
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// LUT_INIT[12] = 1
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// LUT_INIT[13] = 1
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// LUT_INIT[14] = 1
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// LUT_INIT[15] = 1
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(* keep *) SB_LUT4 lut( .O(delay_tap), .I0(const_zero), .I1(const_zero),
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.I2(const_one), .I3(chainin));
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//TODO: is this the right way round??
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defparam lut.LUT_INIT=16'hFF00;
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endmodule // delay_element
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EOT
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synth_ice40
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select -assert-count 1 t:SB_LUT4
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select -assert-count 1 t:SB_CARRY
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select -assert-count 1 t:SB_CARRY a:keep %i
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select -assert-count 1 t:SB_CARRY c:carry %i
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design -reset
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read_verilog -icells <<EOT
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module top(input I3, I2, I1, I0, output O, O2);
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SB_LUT4 #(
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.LUT_INIT(8'b 1001_0110)
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) u0 (
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.I0(I0),
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.I1(I1),
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.I2(I2),
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.I3(),
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.O(O)
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);
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wire CO;
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\$__ICE40_CARRY_WRAPPER #(
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.LUT(~8'b 1001_0110),
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.I3_IS_CI(1'b0)
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) u1 (
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.A(1'b0),
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.B(1'b0),
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.CI(1'b0),
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.I0(),
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.I3(),
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.CO(CO),
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.O(O2)
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);
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endmodule
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EOT
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ice40_opt
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