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171c425cf9
Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
26 lines
805 B
Plaintext
26 lines
805 B
Plaintext
# This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
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arraycells.v inst id[0] of
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dff_different_styles.v
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generate.v combinational loop
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hierdefparam.v inst id[0] of
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i2c_master_tests.v $adff
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macros.v drops modules
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mem2reg.v drops modules
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mem_arst.v $adff
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memory.v $adff
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multiplier.v inst id[0] of
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muxtree.v drops modules
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omsp_dbg_uart.v $adff
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operators.v $pow
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partsel.v drops modules
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process.v drops modules
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realexpr.v drops modules
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scopes.v original verilog issues ( -x where x isn't declared signed)
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sincos.v $adff
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specify.v no code (empty module generates error
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subbytes.v $adff
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task_func.v drops modules
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values.v combinational loop
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vloghammer.v combinational loop
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wreduce.v original verilog issues ( -x where x isn't declared signed)
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