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2e37e62e6b
By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
30 lines
646 B
Verilog
30 lines
646 B
Verilog
module __MISTRAL_MLAB(CLK1, CLK2, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA);
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parameter CFG_ABITS = 5;
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parameter CFG_DBITS = 20;
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input CLK1, CLK2;
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input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
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input [CFG_DBITS-1:0] A1DATA;
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input A1EN;
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output [CFG_DBITS-1:0] B1DATA;
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altsyncram #(
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.operation_mode("dual_port"),
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.ram_block_type("mlab"),
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.widthad_a(CFG_ABITS),
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.width_a(CFG_DBITS),
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.widthad_b(CFG_ABITS),
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.width_b(CFG_DBITS),
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) _TECHMAP_REPLACE_ (
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.address_a(A1ADDR),
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.data_a(A1DATA),
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.wren_a(A1EN),
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.address_b(B1ADDR),
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.q_b(B1DATA),
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.clock0(CLK1),
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.clock1(CLK1),
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);
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endmodule
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