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22 lines
783 B
Verilog
22 lines
783 B
Verilog
module m(input clk, input `SIGN [31:0] data);
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always @(posedge clk)
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// All on a single line to avoid order effects.
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`ifdef BASE_DEC
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$display(":%d:%-d:%+d:%+-d:%0d:%-0d:%+0d:%+-0d:%20d:%-20d:%+20d:%+-20d:%020d:%-020d:%+020d:%+-020d:",
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data, data, data, data, data, data, data, data, data, data, data, data, data, data, data, data);
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`endif
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`ifdef BASE_HEX
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$display(":%h:%-h:%0h:%-0h:%20h:%-20h:%020h:%-020h:",
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data, data, data, data, data, data, data, data);
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`endif
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`ifdef BASE_OCT
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$display(":%o:%-o:%0o:%-0o:%20o:%-20o:%020o:%-020o:",
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data, data, data, data, data, data, data, data);
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`endif
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`ifdef BASE_BIN
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$display(":%b:%-b:%0b:%-0b:%20b:%-20b:%020b:%-020b:",
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data, data, data, data, data, data, data, data);
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`endif
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endmodule
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