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https://github.com/YosysHQ/yosys
synced 2025-04-06 09:34:09 +00:00
15f35d6754
- Add support for: *=, /=, %=, <<=, >>=, <<<=, >>>= - Unify existing support for: +=, -=, &=, |=, ^=
24 lines
380 B
Systemverilog
24 lines
380 B
Systemverilog
`define TEST(name, asgnop)\
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module test_``name ( \
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input logic [3:0] a, b, \
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output logic [3:0] c \
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); \
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always @* begin \
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c = a; \
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c asgnop b; \
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end \
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endmodule
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`TEST(add, +=)
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`TEST(sub, -=)
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`TEST(mul, *=)
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`TEST(div, /=)
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`TEST(mod, %=)
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`TEST(bit_and, &=)
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`TEST(bit_or , |=)
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`TEST(bit_xor, ^=)
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`TEST(shl, <<=)
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`TEST(shr, >>=)
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`TEST(sshl, <<<=)
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`TEST(sshr, >>>=)
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