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yosys/backends
2021-05-25 02:07:25 +02:00
..
aiger abc9: fix SCC issues (#2694) 2021-03-29 22:01:57 -07:00
blif
btor Reject wide ports in some passes that will never support them. 2021-05-25 02:07:25 +02:00
cxxrtl cxxrtl: don't assert on edge sync rules tied to a constant. 2021-03-07 14:29:30 +00:00
edif
firrtl Reject wide ports in some passes that will never support them. 2021-05-25 02:07:25 +02:00
intersynth
json json: Improve the "processes in module" message a bit. 2021-03-23 15:53:49 +01:00
protobuf
rtlil rtlil: Fix process memwr roundtrip. 2021-03-23 19:49:47 +01:00
simplec
smt2 Reject wide ports in some passes that will never support them. 2021-05-25 02:07:25 +02:00
smv btor, smt2, smv: Add a hint on how to deal with funny FF types. 2021-02-25 22:04:04 +01:00
spice add buffer option to spice backend 2021-01-13 17:24:28 +01:00
table
verilog kernel/rtlil: Extract some helpers for checking memory cell types. 2021-05-22 21:43:00 +02:00