Claire Xenia Wolf fe9689c136 Fixed Verific parser error in ice40 cell library ... non-net output port 'Q' cannot be initialized at declaration in SystemVerilog mode		2021-10-19 12:33:18 +02:00
..
tests
.gitignore
abc9_model.v
arith_map.v
brams.txt
brams_init.py
brams_map.v
cells_map.v
cells_sim.v	Fixed Verific parser error in ice40 cell library	2021-10-19 12:33:18 +02:00
dsp_map.v
ff_map.v
ice40_braminit.cc
ice40_opt.cc
latches_map.v
Makefile.inc
synth_ice40.cc	opt_lut: Allow more than one -dlogic per cell type.	2021-07-29 17:30:07 +02:00