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yosys/tests/ice40/add_sub_top.v
2019-08-20 07:50:05 +03:00

14 lines
133 B
Verilog

module top
(
input [3:0] x,
input [3:0] y,
output [3:0] A,
output [3:0] B
);
assign A = x + y;
assign B = x - y;
endmodule