Claire Xenia Wolf fe9689c136 Fixed Verific parser error in ice40 cell library ... non-net output port 'Q' cannot be initialized at declaration in SystemVerilog mode		2021-10-19 12:33:18 +02:00
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achronix
anlogic
common	Hook up $aldff support in various passes.	2021-10-02 21:01:21 +02:00
coolrunner2
easic
ecp5	abc9: replace cell type/parameters if derived type already processed (#2991)	2021-09-09 10:05:55 -07:00
efinix
gowin	Gowin: deal with active-low tristate (#2971)	2021-08-20 21:21:06 +02:00
greenpak4
ice40	Fixed Verific parser error in ice40 cell library	2021-10-19 12:33:18 +02:00
intel
intel_alm	CycloneV: Add (passthrough) support for cyclonev_oscillator	2021-10-17 20:00:03 +02:00
machxo2
nexus	Gowin: deal with active-low tristate (#2971)	2021-08-20 21:21:06 +02:00
quicklogic
sf2
xilinx
.gitignore