mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
12 lines
167 B
Verilog
12 lines
167 B
Verilog
module top (
|
|
input clk,
|
|
output reg [7:0] cnt
|
|
);
|
|
initial cnt = 0;
|
|
always @(posedge clk) begin
|
|
if (cnt < 20)
|
|
cnt <= cnt + 1;
|
|
else
|
|
cnt <= 0;
|
|
end
|
|
endmodule
|