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100 lines
1.3 KiB
Text
100 lines
1.3 KiB
Text
read_verilog << EOT
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module top(...);
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input [3:0] ra;
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input [3:0] wa;
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input [15:0] wd;
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output [15:0] rd;
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input en, clk;
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reg [15:0] mem[3:9];
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always @(posedge clk)
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if (en)
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mem[wa] <= wd;
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assign rd = mem[ra];
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt_clean
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memory_map
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design -stash gate
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read_verilog << EOT
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module top(...);
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input [3:0] ra;
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input [3:0] wa;
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input [15:0] wd;
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output reg [15:0] rd;
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input en, clk;
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reg [15:0] \mem[3] ;
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reg [15:0] \mem[4] ;
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reg [15:0] \mem[5] ;
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reg [15:0] \mem[6] ;
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reg [15:0] \mem[7] ;
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reg [15:0] \mem[8] ;
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reg [15:0] \mem[9] ;
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always @(posedge clk) begin
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if (en && wa == 3)
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\mem[3] <= wd;
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if (en && wa == 4)
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\mem[4] <= wd;
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if (en && wa == 5)
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\mem[5] <= wd;
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if (en && wa == 6)
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\mem[6] <= wd;
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if (en && wa == 7)
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\mem[7] <= wd;
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if (en && wa == 8)
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\mem[8] <= wd;
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if (en && wa == 9)
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\mem[9] <= wd;
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end
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always @* begin
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rd = 16'bx;
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if (ra == 3)
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rd = \mem[3] ;
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if (ra == 4)
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rd = \mem[4] ;
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if (ra == 5)
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rd = \mem[5] ;
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if (ra == 6)
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rd = \mem[6] ;
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if (ra == 7)
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rd = \mem[7] ;
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if (ra == 8)
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rd = \mem[8] ;
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if (ra == 9)
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rd = \mem[9] ;
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end
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt_clean
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design -stash gold
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design -copy-from gold -as gold A:top
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design -copy-from gate -as gate A:top
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equiv_make gold gate equiv
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equiv_induct -undef equiv
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equiv_status -assert equiv
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