mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
120 lines
5.6 KiB
Python
120 lines
5.6 KiB
Python
#!/usr/bin/env python3
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import argparse
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import sys
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import random
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from contextlib import contextmanager
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# set to 'True' to compare verific with yosys
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test_verific = False
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@contextmanager
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def redirect_stdout(new_target):
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old_target, sys.stdout = sys.stdout, new_target
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try:
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yield new_target
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finally:
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sys.stdout = old_target
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def random_expr(variables):
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c = random.choice(['bin', 'uni', 'var', 'const'])
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if c == 'bin':
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op = random.choice(['+', '-', '*', '<', '<=', '==', '!=', '>=', '>', '<<', '>>', '<<<', '>>>', '|', '&', '^', '~^', '||', '&&'])
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return "(%s %s %s)" % (random_expr(variables), op, random_expr(variables))
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if c == 'uni':
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op = random.choice(['+', '-', '~', '|', '&', '^', '~^', '!', '$signed', '$unsigned'])
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return "%s(%s)" % (op, random_expr(variables))
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if c == 'var':
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return random.choice(variables)
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if c == 'const':
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bits = random.randint(1, 32)
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return "%d'd%s" % (bits, random.randint(0, 2**bits-1))
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raise AssertionError
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parser = argparse.ArgumentParser(formatter_class = argparse.ArgumentDefaultsHelpFormatter)
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parser.add_argument('-S', '--seed', type = int, help = 'seed for PRNG')
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parser.add_argument('-c', '--count', type = int, default = 50, help = 'number of test cases to generate')
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args = parser.parse_args()
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seed = args.seed
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if seed is None:
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seed = random.randrange(sys.maxsize)
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print("PRNG seed: %d" % seed)
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random.seed(seed)
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for idx in range(args.count):
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with open('temp/uut_%05d.v' % idx, 'w') as f:
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with redirect_stdout(f):
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rst2 = random.choice([False, True])
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if rst2:
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print('module uut_%05d(clk, rst1, rst2, rst, a, b, c, x, y, z);' % (idx))
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print(' input clk, rst1, rst2;')
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print(' output rst;')
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print(' assign rst = rst1 || rst2;')
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else:
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print('module uut_%05d(clk, rst, a, b, c, x, y, z);' % (idx))
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print(' input clk, rst;')
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variables=['a', 'b', 'c', 'x', 'y', 'z']
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print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' output reg%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' output reg%s [%d:0] y;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' output reg%s [%d:0] z;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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state_bits = random.randint(5, 16);
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print(' %sreg [%d:0] state;' % (random.choice(['', '(* fsm_encoding = "one-hot" *)',
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'(* fsm_encoding = "binary" *)']), state_bits-1))
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states=[]
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for i in range(random.randint(2, 10)):
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n = random.randint(0, 2**state_bits-1)
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if n not in states:
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states.append(n)
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print(' always @(posedge clk) begin')
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print(' if (%s) begin' % ('rst1' if rst2 else 'rst'))
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print(' x <= %d;' % random.randint(0, 2**31-1))
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print(' y <= %d;' % random.randint(0, 2**31-1))
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print(' z <= %d;' % random.randint(0, 2**31-1))
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print(' state <= %d;' % random.choice(states))
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print(' end else begin')
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print(' case (state)')
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for state in states:
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print(' %d: begin' % state)
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for var in ('x', 'y', 'z'):
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print(' %s <= %s;' % (var, random_expr(variables)))
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next_states = states[:]
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for i in range(random.randint(0, len(states))):
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next_state = random.choice(next_states)
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next_states.remove(next_state)
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print(' if ((%s) %s (%s)) state <= %s;' % (random_expr(variables),
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random.choice(['<', '<=', '>=', '>']), random_expr(variables), next_state))
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print(' end')
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print(' endcase')
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if rst2:
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print(' if (rst2) begin')
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print(' x <= a;')
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print(' y <= b;')
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print(' z <= c;')
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print(' state <= %d;' % random.choice(states))
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print(' end')
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print(' end')
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print(' end')
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print('endmodule')
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with open('temp/uut_%05d.ys' % idx, 'w') as f:
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with redirect_stdout(f):
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if test_verific:
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print('read_verilog temp/uut_%05d.v' % idx)
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print('proc;; rename uut_%05d gold' % idx)
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print('verific -vlog2k temp/uut_%05d.v' % idx)
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print('verific -import uut_%05d' % idx)
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print('rename uut_%05d gate' % idx)
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else:
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print('read_verilog temp/uut_%05d.v' % idx)
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print('proc;;')
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print('copy uut_%05d gold' % idx)
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print('rename uut_%05d gate' % idx)
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print('cd gate')
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print('opt; wreduce; share%s; opt; fsm;;' % random.choice(['', ' -aggressive']))
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print('cd ..')
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print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
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print('sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 %s_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter' % ('gold' if rst2 else 'in'))
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