mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-11-04 05:19:11 +00:00 
			
		
		
		
	
		
			
				
	
	
		
			12 lines
		
	
	
	
		
			197 B
		
	
	
	
		
			Verilog
		
	
	
	
	
	
			
		
		
	
	
			12 lines
		
	
	
	
		
			197 B
		
	
	
	
		
			Verilog
		
	
	
	
	
	
module top;
 | 
						|
    mid mid_uut ();
 | 
						|
endmodule
 | 
						|
 | 
						|
module mid ();
 | 
						|
    bot bot_uut ();
 | 
						|
endmodule
 | 
						|
 | 
						|
module bot ();
 | 
						|
    initial $display("%%l: %l\n%%m: %m");
 | 
						|
    always $display("%%l: %l\n%%m: %m");
 | 
						|
endmodule
 |