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35 lines
472 B
Verilog
35 lines
472 B
Verilog
module explicit();
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reg clk,d,rst,pre;
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wire q;
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// Here q_bar is not connected
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// We can connect ports in any order
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dff u0 (
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.q (q),
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.d (d),
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.clk (clk),
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.q_bar (),
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.rst (rst),
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.pre (pre)
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);
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endmodule
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// D fli-flop
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module dff (q, q_bar, clk, d, rst, pre);
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input clk, d, rst, pre;
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output q, q_bar;
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reg q;
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assign q_bar = ~q;
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always @ (posedge clk)
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if (rst == 1'b1) begin
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q <= 0;
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end else if (pre == 1'b1) begin
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q <= 1;
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end else begin
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q <= d;
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end
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endmodule
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