mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
471 lines
10 KiB
C++
471 lines
10 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef SIGTOOLS_H
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#define SIGTOOLS_H
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#include "kernel/yosys.h"
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YOSYS_NAMESPACE_BEGIN
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struct SigPool
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{
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struct bitDef_t : public std::pair<RTLIL::Wire*, int> {
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bitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }
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bitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }
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[[nodiscard]] Hasher hash_into(Hasher h) const {
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h.eat(first->name);
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h.eat(second);
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return h;
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}
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};
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pool<bitDef_t> bits;
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void clear()
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{
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bits.clear();
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}
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void add(const RTLIL::SigSpec &sig)
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{
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for (auto &bit : sig)
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if (bit.wire != NULL)
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bits.insert(bit);
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}
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void add(const SigPool &other)
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{
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for (auto &bit : other.bits)
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bits.insert(bit);
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}
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void del(const RTLIL::SigSpec &sig)
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{
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for (auto &bit : sig)
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if (bit.wire != NULL)
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bits.erase(bit);
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}
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void del(const SigPool &other)
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{
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for (auto &bit : other.bits)
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bits.erase(bit);
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}
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void expand(const RTLIL::SigSpec &from, const RTLIL::SigSpec &to)
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{
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log_assert(GetSize(from) == GetSize(to));
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for (int i = 0; i < GetSize(from); i++) {
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bitDef_t bit_from(from[i]), bit_to(to[i]);
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if (bit_from.first != NULL && bit_to.first != NULL && bits.count(bit_from) > 0)
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bits.insert(bit_to);
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}
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}
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RTLIL::SigSpec extract(const RTLIL::SigSpec &sig) const
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{
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RTLIL::SigSpec result;
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for (auto &bit : sig)
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if (bit.wire != NULL && bits.count(bit))
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result.append(bit);
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return result;
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}
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RTLIL::SigSpec remove(const RTLIL::SigSpec &sig) const
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{
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RTLIL::SigSpec result;
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for (auto &bit : sig)
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if (bit.wire != NULL && bits.count(bit) == 0)
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result.append(bit);
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return result;
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}
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bool check(const RTLIL::SigBit &bit) const
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{
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return bit.wire != NULL && bits.count(bit);
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}
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bool check_any(const RTLIL::SigSpec &sig) const
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{
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for (auto &bit : sig)
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if (bit.wire != NULL && bits.count(bit))
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return true;
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return false;
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}
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bool check_all(const RTLIL::SigSpec &sig) const
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{
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for (auto &bit : sig)
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if (bit.wire != NULL && bits.count(bit) == 0)
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return false;
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return true;
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}
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RTLIL::SigSpec export_one() const
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{
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for (auto &bit : bits)
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return RTLIL::SigSpec(bit.first, bit.second);
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return RTLIL::SigSpec();
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}
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RTLIL::SigSpec export_all() const
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{
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pool<RTLIL::SigBit> sig;
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for (auto &bit : bits)
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sig.insert(RTLIL::SigBit(bit.first, bit.second));
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return sig;
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}
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size_t size() const
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{
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return bits.size();
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}
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};
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template <typename T, class Compare = void>
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struct SigSet
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{
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static_assert(!std::is_same<Compare,void>::value, "Default value for `Compare' class not found for SigSet<T>. Please specify.");
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struct bitDef_t : public std::pair<RTLIL::Wire*, int> {
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bitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }
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bitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }
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[[nodiscard]] Hasher hash_into(Hasher h) const {
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h.eat(first->name);
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h.eat(second);
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return h;
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}
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};
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dict<bitDef_t, std::set<T, Compare>> bits;
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void clear()
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{
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bits.clear();
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}
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void insert(const RTLIL::SigSpec &sig, T data)
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{
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for (const auto &bit : sig)
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if (bit.wire != NULL)
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bits[bit].insert(data);
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}
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void insert(const RTLIL::SigSpec& sig, const std::set<T> &data)
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{
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for (const auto &bit : sig)
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if (bit.wire != NULL)
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bits[bit].insert(data.begin(), data.end());
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}
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void erase(const RTLIL::SigSpec& sig)
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{
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for (const auto &bit : sig)
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if (bit.wire != NULL)
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bits[bit].clear();
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}
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void erase(const RTLIL::SigSpec &sig, T data)
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{
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for (const auto &bit : sig)
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if (bit.wire != NULL)
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bits[bit].erase(data);
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}
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void erase(const RTLIL::SigSpec &sig, const std::set<T> &data)
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{
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for (const auto &bit : sig)
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if (bit.wire != NULL)
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bits[bit].erase(data.begin(), data.end());
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}
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void find(const RTLIL::SigSpec &sig, std::set<T> &result)
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{
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for (const auto &bit : sig)
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if (bit.wire != NULL) {
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auto &data = bits[bit];
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result.insert(data.begin(), data.end());
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}
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}
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void find(const RTLIL::SigSpec &sig, pool<T> &result)
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{
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for (const auto &bit : sig)
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if (bit.wire != NULL) {
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auto &data = bits[bit];
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result.insert(data.begin(), data.end());
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}
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}
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std::set<T> find(const RTLIL::SigSpec &sig)
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{
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std::set<T> result;
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find(sig, result);
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return result;
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}
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bool has(const RTLIL::SigSpec &sig)
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{
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for (auto &bit : sig)
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if (bit.wire != NULL && bits.count(bit))
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return true;
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return false;
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}
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};
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template<typename T>
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class SigSet<T, typename std::enable_if<!std::is_pointer<T>::value>::type> : public SigSet<T, std::less<T>> {};
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template<typename T>
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using sort_by_name_id_guard = typename std::enable_if<std::is_same<T,RTLIL::Cell*>::value>::type;
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template<typename T>
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class SigSet<T, sort_by_name_id_guard<T>> : public SigSet<T, RTLIL::sort_by_name_id<typename std::remove_pointer<T>::type>> {};
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struct SigMapView
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{
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mfp<SigBit> database;
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// Modify bit to its representative
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void apply(RTLIL::SigBit &bit) const
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{
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bit = database.find(bit);
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}
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void apply(RTLIL::SigSpec &sig) const
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{
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for (auto &bit : sig)
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apply(bit);
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}
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RTLIL::SigBit operator()(RTLIL::SigBit bit) const
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{
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apply(bit);
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return bit;
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}
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RTLIL::SigSpec operator()(RTLIL::SigSpec sig) const
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{
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apply(sig);
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return sig;
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}
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RTLIL::SigSpec operator()(RTLIL::Wire *wire) const
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{
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SigSpec sig(wire);
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apply(sig);
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return sig;
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}
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};
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/**
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* SigMap wraps a union-find "database"
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* to map SigBits of a module to canonical representative SigBits.
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* SigBits that are connected share a set in the underlying database.
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* If a SigBit has a const state (impl: bit.wire is nullptr),
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* it's promoted to a representative.
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*/
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struct SigMap final : public SigMapView
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{
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SigMap(RTLIL::Module *module = NULL)
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{
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if (module != NULL)
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set(module);
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}
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void swap(SigMap &other)
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{
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database.swap(other.database);
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}
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void clear()
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{
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database.clear();
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}
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// Rebuild SigMap for all connections in module
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void set(RTLIL::Module *module)
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{
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int bitcount = 0;
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for (auto &it : module->connections())
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bitcount += it.first.size();
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database.clear();
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database.reserve(bitcount);
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for (auto &it : module->connections())
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add(it.first, it.second);
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}
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// Add connections from "from" to "to", bit-by-bit
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void add(const RTLIL::SigSpec& from, const RTLIL::SigSpec& to)
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{
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log_assert(GetSize(from) == GetSize(to));
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for (int i = 0; i < GetSize(from); i++)
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{
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int bfi = database.lookup(from[i]);
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int bti = database.lookup(to[i]);
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const RTLIL::SigBit &bf = database[bfi];
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const RTLIL::SigBit &bt = database[bti];
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if (bf.wire || bt.wire)
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{
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database.imerge(bfi, bti);
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if (bf.wire == nullptr)
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database.ipromote(bfi);
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if (bt.wire == nullptr)
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database.ipromote(bti);
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}
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}
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}
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// Add sig as disconnected from anything
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void add(const RTLIL::SigBit &bit)
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{
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const auto &b = database.find(bit);
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if (b.wire != nullptr)
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database.promote(bit);
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}
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void add(const RTLIL::SigSpec &sig)
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{
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for (const auto &bit : sig)
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add(bit);
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}
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inline void add(Wire *wire) { return add(RTLIL::SigSpec(wire)); }
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// All non-const bits
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RTLIL::SigSpec allbits() const
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{
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RTLIL::SigSpec sig;
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for (const auto &bit : database)
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if (bit.wire != nullptr)
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sig.append(bit);
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return sig;
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}
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};
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/**
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* SiValgMap wraps a union-find "database" to map SigBits of a module to
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* canonical representative SigBits plus some optional Val value associated with the bits.
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* Val has a commutative, associative, idempotent operator|=, a default constructor
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* which constructs an identity element, and a copy constructor.
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* SigBits that are connected share a set in the underlying database;
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* the associated value is the "sum" of all the values associated with the contributing bits.
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* If any of the SigBits in a set are a constant, the canonical SigBit is a constant.
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*/
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template <class Val>
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struct SigValMap final : public SigMapView
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{
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dict<SigBit, Val> values;
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void swap(SigValMap<Val> &other)
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{
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database.swap(other.database);
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values.swap(other.values);
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}
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void clear()
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{
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database.clear();
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values.clear();
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}
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// Rebuild SigMap for all connections in module
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void set(RTLIL::Module *module)
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{
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int bitcount = 0;
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for (auto &it : module->connections())
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bitcount += it.first.size();
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database.clear();
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values.clear();
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database.reserve(bitcount);
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for (auto &it : module->connections())
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add(it.first, it.second);
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}
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// Add connections from "from" to "to", bit-by-bit.
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void add(const RTLIL::SigSpec& from, const RTLIL::SigSpec& to)
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{
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log_assert(GetSize(from) == GetSize(to));
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for (int i = 0; i < GetSize(from); i++)
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{
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int bfi = database.lookup(from[i]);
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int bti = database.lookup(to[i]);
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if (bfi == bti) {
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continue;
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}
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const RTLIL::SigBit &bf = database[bfi];
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const RTLIL::SigBit &bt = database[bti];
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if (bf.wire == nullptr) {
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// bf is constant so make it the canonical representative.
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database.imerge(bti, bfi);
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merge_value(bt, bf);
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} else {
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// Make bt the canonical representative.
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database.imerge(bfi, bti);
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merge_value(bf, bt);
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}
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}
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}
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void addVal(const RTLIL::SigBit &bit, const Val &val)
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{
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values[database.find(bit)] |= val;
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}
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void addVal(const RTLIL::SigSpec &sig, const Val &val)
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{
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for (const auto &bit : sig)
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addVal(bit, val);
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}
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Val apply_and_get_value(RTLIL::SigBit &bit) const
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{
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bit = database.find(bit);
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auto it = values.find(bit);
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return it == values.end() ? Val() : it->second;
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}
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private:
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void merge_value(const RTLIL::SigBit &from, const RTLIL::SigBit &to)
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{
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auto it = values.find(from);
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if (it == values.end()) {
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return;
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}
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// values[to] could resize the underlying `entries` so
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// finish using `it` first.
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Val v = it->second;
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values.erase(it);
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values[to] |= v;
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}
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};
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YOSYS_NAMESPACE_END
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#endif /* SIGTOOLS_H */
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