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yosys/techlibs/greenpak4
2019-02-26 09:40:46 -08:00
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cells_blackbox.v
cells_latch.v
cells_map.v techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module 2019-02-26 09:40:46 -08:00
cells_sim.v Refactoring: moved modules still in cells_sim to cells_sim_wip 2017-09-01 06:44:15 -07:00
cells_sim_ams.v
cells_sim_digital.v Fixed typo in error message 2017-09-01 06:45:10 -07:00
cells_sim_wip.v
gp_dff.lib
greenpak4_dffinv.cc
Makefile.inc Added blackbox $__COUNT_ cell model 2017-09-01 06:44:28 -07:00
synth_greenpak4.cc