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331ac5285f
Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions.
16 lines
277 B
Plaintext
16 lines
277 B
Plaintext
read_verilog -sv initval.v
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proc; async2sync;;
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sat -seq 10 -prove-asserts
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design -reset
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read_verilog -icells <<EOT
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module top(input clk, i, output [1:0] o);
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(* init = 2'bx0 *)
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wire [1:0] o;
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assign o[1] = o[0];
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$_DFF_P_ dff (.C(clk), .D(i), .Q(o[0]));
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endmodule
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EOT
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sat -seq 1
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