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331ac5285f
Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions.
16 lines
626 B
Plaintext
16 lines
626 B
Plaintext
read_verilog -sv meminit.v
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chparam -set DEPTH_LOG2 3 -set WIDTH 36
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prep
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opt_dff
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prep -rdff
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synth_quicklogic -family qlf_k6n10f -run map_bram:map_bram
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select -assert-none t:$mem_v2 t:$mem
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select -assert-count 1 t:TDP36K
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select -assert-count 1 t:TDP36K a:is_split=0 %i
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select -assert-count 1 t:TDP36K a:was_split_candidate=0 %i
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read_verilog +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
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prep
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async2sync
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hierarchy -top top
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sim -assert -q -n 12 -clock clk
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