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34 lines
711 B
Verilog
34 lines
711 B
Verilog
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// The M9K
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// --------
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// TODO
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module MISTRAL_M9K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 10;
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parameter CFG_DBITS = 10;
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input CLK1;
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input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
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input [CFG_DBITS-1:0] A1DATA;
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input A1EN, B1EN;
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output reg [CFG_DBITS-1:0] B1DATA;
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reg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = 0;
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specify
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$setup(A1ADDR, posedge CLK1, 0);
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$setup(A1DATA, posedge CLK1, 0);
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if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 0;
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endspecify
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always @(posedge CLK1) begin
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if (A1EN)
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mem[(A1ADDR + 1) * CFG_DBITS - 1 : A1ADDR * CFG_DBITS] <= A1DATA;
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if (B1EN)
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B1DATA <= mem[(B1ADDR + 1) * CFG_DBITS - 1 : B1ADDR * CFG_DBITS];
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end
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endmodule
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