mirror of
https://github.com/YosysHQ/yosys
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151 lines
3.2 KiB
Verilog
151 lines
3.2 KiB
Verilog
module \$__NX_MUL36X36 (input [35:0] A, input [35:0] B, output [71:0] Y);
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parameter A_WIDTH = 36;
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parameter B_WIDTH = 36;
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parameter Y_WIDTH = 72;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT36X36 #(
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.REGINPUTA("BYPASS"),
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.REGINPUTB("BYPASS"),
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.REGOUTPUT("BYPASS")
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) _TECHMAP_REPLACE_ (
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.A(A), .B(B),
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.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),
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.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),
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.Z(Y)
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);
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endmodule
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module \$__NX_MUL36X18 (input [35:0] A, input [17:0] B, output [53:0] Y);
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parameter A_WIDTH = 36;
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parameter B_WIDTH = 18;
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parameter Y_WIDTH = 54;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT18X36 #(
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.REGINPUTA("BYPASS"),
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.REGINPUTB("BYPASS"),
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.REGOUTPUT("BYPASS")
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) _TECHMAP_REPLACE_ (
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.A(B), .B(A),
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.SIGNEDA(B_SIGNED ? 1'b1 : 1'b0),
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.SIGNEDB(A_SIGNED ? 1'b1 : 1'b0),
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.Z(Y)
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);
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endmodule
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module \$__NX_MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
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parameter A_WIDTH = 18;
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parameter B_WIDTH = 18;
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parameter Y_WIDTH = 36;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT18X18 #(
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.REGINPUTA("BYPASS"),
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.REGINPUTB("BYPASS"),
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.REGOUTPUT("BYPASS")
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) _TECHMAP_REPLACE_ (
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.A(A), .B(B),
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.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),
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.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),
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.Z(Y)
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);
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endmodule
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module \$__NX_MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y);
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parameter A_WIDTH = 9;
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parameter B_WIDTH = 9;
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parameter Y_WIDTH = 18;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT9X9 #(
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.REGINPUTA("BYPASS"),
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.REGINPUTB("BYPASS"),
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.REGOUTPUT("BYPASS")
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) _TECHMAP_REPLACE_ (
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.A(A), .B(B),
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.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),
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.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),
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.Z(Y)
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);
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endmodule
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module \$__NX_MAC18X18 (input [17:0] A, input [17:0] B, input [47:0] C, output [53:0] Y);
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parameter A_WIDTH = 18;
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parameter B_WIDTH = 18;
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parameter C_WIDTH = 48;
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parameter Y_WIDTH = 48;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter SUBTRACT = 0;
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MULTADDSUB18X18 #(
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.REGINPUTA("BYPASS"),
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.REGINPUTB("BYPASS"),
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.REGINPUTC("BYPASS"),
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.REGOUTPUT("BYPASS")
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) _TECHMAP_REPLACE_ (
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.A(A),
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.B(B),
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.C({6'b0, C}),
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.SIGNED(A_SIGNED ? 1'b1 : 1'b0),
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.ADDSUB(SUBTRACT ? 1'b1 : 1'b0),
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.Z(Y)
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);
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endmodule
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module \$__NX_PREADD18X18 (input [17:0] A, input [17:0] B, input [17:0] C, input CLK, output [35:0] Y);
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parameter PIPELINED = 0;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter C_SIGNED = 0;
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MULTPREADD18X18 #(
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.REGINPUTA("BYPASS"),
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.REGINPUTB("BYPASS"),
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.REGINPUTC("BYPASS"),
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.REGOUTPUT(PIPELINED ? "REGISTER" : "BYPASS")
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) _TECHMAP_REPLACE_ (
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.A(A),
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.B(B),
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.C(C),
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.CLK(CLK),
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.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),
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.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),
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.SIGNEDC(C_SIGNED ? 1'b1 : 1'b0),
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.Z(Y)
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);
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endmodule
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module \$__NX_MAC9X9WIDE_4LANE (input [8:0] A0, B0, A1, B1, A2, B2, A3, B3, output [53:0] Y);
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parameter SIGNED = 0;
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MULTADDSUB9X9WIDE #(
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.REGINPUTAB0("BYPASS"),
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.REGINPUTAB1("BYPASS"),
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.REGINPUTAB2("BYPASS"),
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.REGINPUTAB3("BYPASS"),
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.REGINPUTC("BYPASS"),
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.REGOUTPUT("BYPASS")
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) _TECHMAP_REPLACE_ (
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.A0(A0), .B0(B0),
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.A1(A1), .B1(B1),
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.A2(A2), .B2(B2),
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.A3(A3), .B3(B3),
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.C(54'b0),
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.SIGNED(SIGNED ? 1'b1 : 1'b0),
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.ADDSUB(4'b0000),
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.Z(Y)
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);
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endmodule
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