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aiger
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arch
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fabulous: Allow adding extra custom prims and map rules
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2022-11-17 13:34:58 +01:00 |
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asicworld
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bind
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Add support for parsing the SystemVerilog 'bind' construct
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2021-07-16 09:31:39 -04:00 |
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blif
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Adding check for BLIF names command input plane size.
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2022-08-21 23:18:20 -05:00 |
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bram
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Fix the tests we just broke
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2021-12-10 00:22:37 +01:00 |
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errors
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fsm
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hana
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liberty
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lut
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memfile
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memlib
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Add memory_libmap tests.
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2022-05-18 17:32:56 +02:00 |
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memories
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Fix the tests we just broke
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2021-12-10 00:22:37 +01:00 |
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opt
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simplemap: Map $xnor to $_XNOR_ cells
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2022-11-29 19:06:45 +01:00 |
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opt_share
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proc
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proc_rom: Add special handling of const-0 address bits.
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2022-05-18 17:32:30 +02:00 |
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realmath
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rpc
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sat
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Proper example code
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2022-03-14 15:39:11 +01:00 |
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select
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share
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sim
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Replace GNU specific invocation of basename(1) with the equivalent
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2022-10-23 11:02:18 +13:00 |
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simple
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verilog: Support module-scoped task/function calls
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2022-10-29 15:14:11 -04:00 |
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simple_abc9
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abc9: fix SCC issues (#2694)
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2021-03-29 22:01:57 -07:00 |
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smv
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sva
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verific: Use new value change logic also for $stable of wide signals.
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2022-05-11 13:05:27 +02:00 |
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svinterfaces
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Resolve package types in interfaces (#3658)
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2023-02-12 18:25:39 -05:00 |
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svtypes
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Resolve struct member package types
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2023-01-29 13:51:44 -05:00 |
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techmap
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add pmux option to bmuxmap for better fsm detection with verific frontend
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2023-01-30 16:12:53 +01:00 |
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tools
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support file locations containing spaces
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2022-08-08 20:30:50 +02:00 |
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unit
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various
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backends/rtlil: Do not shorten a value with z bits to 'x
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2023-01-29 14:02:25 +01:00 |
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verilog
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verilog: fix width/sign detection for functions
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2022-05-30 16:45:39 -04:00 |
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vloghtb
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Use HTTPS for website links, gatecat email
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2021-06-09 12:16:56 +02:00 |
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xprop
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tests: in xprop tests, use MAKE variable if set
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2023-02-10 15:01:04 +01:00 |
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gen-tests-makefile.sh
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support file locations containing spaces
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2022-08-08 20:30:50 +02:00 |
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