yosys/tests/lut/map_mux.v at 1248af1e022e38211febf510976a0799cb767524 - mirrors/yosys - Libre-Chip.org

mirrors/yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-10-30 19:22:31 +00:00

whitequark 9ef078848a gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

2018-12-05 17:13:27 +00:00

5 lines

82 B

Verilog

Raw Blame History

 module top(...);
     input a, b, s;
     output y;
     assign y = s?a:b;
 endmodule