Miodrag Milanovic ced2521b03 Convert gen-tests shell script to python		2026-04-16 11:00:44 +02:00
..
add_sub.ys	Fix tests due to ABC improvements	2026-03-30 15:23:27 +01:00
adffs.ys
bug1459.ys	Add testcase from #1459	2020-01-06 16:22:22 -08:00
bug1598.ys
bug1630.il.gz	Add #1630 testcase	2020-01-13 21:27:53 -08:00
bug1630.ys	Remove references to ilang	2024-11-05 12:36:31 +13:00
bug1836.mem	Addings tests for #1836 and #3205	2023-02-21 05:23:14 +13:00
bug1836.ys	Genericising bug1836.ys	2023-02-21 05:23:16 +13:00
bug2409.ys	memory_dff: Fix needlessly duplicating enable bits.	2020-10-22 13:03:42 +02:00
bug2731.ys	abc9: replace cell type/parameters if derived type already processed (#2991)	2021-09-09 10:05:55 -07:00
counter.ys	ice40, ecp5, gowin: enable ABC9 by default	2023-11-13 15:28:13 +00:00
dffs.ys
dpram.v
dpram.ys
fsm.ys	Replace opt_rmdff with opt_dff.	2020-08-07 13:21:03 +02:00
generate_mk.py	Convert gen-tests shell script to python	2026-04-16 11:00:44 +02:00
latches.ys
latches_abc9.ys	tests: tidy up testcase	2020-06-03 08:41:55 -07:00
logic.ys
lutram.ys	Fix tests due to ABC improvements	2026-03-30 15:23:27 +01:00
macc.v
macc.ys	Do not do call equiv_opt when no sim model exists	2019-12-31 18:40:30 -08:00
memories.ys	Testing TDP synth mapping	2023-02-21 05:23:15 +13:00
mul.ys	Do not do call equiv_opt when no sim model exists	2019-12-31 18:40:30 -08:00
mux.ys	Update tests	2023-06-09 14:41:45 +02:00
opt_lut_ins.ys	Update opt_lut_ins and stat for analogdevices and remove ecp5	2026-03-06 09:10:36 +01:00
rom.v
rom.ys
shifter.ys
tribuf.ys