mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-12 20:18:20 +00:00
110 lines
2.8 KiB
Verilog
110 lines
2.8 KiB
Verilog
/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */
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(* top = 1 *)
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(* src = "latches.v:27" *)
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module top(clk, clr, pre, a, b, b1, b2);
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(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:105" *)
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wire _0_;
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(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:105" *)
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wire _1_;
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(* src = "latches.v:31" *)
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input a;
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(* src = "latches.v:32" *)
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output b;
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(* src = "latches.v:32" *)
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output b1;
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(* src = "latches.v:32" *)
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output b2;
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(* src = "latches.v:28" *)
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input clk;
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(* src = "latches.v:29" *)
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input clr;
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(* src = "latches.v:30" *)
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input pre;
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(* src = "latches.v:43|latches.v:9" *)
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wire \u_latchn.d ;
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(* src = "latches.v:43|latches.v:9" *)
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wire \u_latchn.en ;
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(* src = "latches.v:43|latches.v:9" *)
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wire \u_latchn.q ;
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(* src = "latches.v:36|latches.v:2" *)
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wire \u_latchp.d ;
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(* src = "latches.v:36|latches.v:2" *)
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wire \u_latchp.en ;
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(* src = "latches.v:36|latches.v:2" *)
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wire \u_latchp.q ;
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(* src = "latches.v:50|latches.v:16" *)
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wire \u_latchsr.clr ;
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(* src = "latches.v:50|latches.v:16" *)
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wire \u_latchsr.d ;
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(* src = "latches.v:50|latches.v:16" *)
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wire \u_latchsr.en ;
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(* src = "latches.v:50|latches.v:16" *)
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wire \u_latchsr.pre ;
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(* src = "latches.v:50|latches.v:16" *)
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wire \u_latchsr.q ;
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(* module_not_derived = 32'd1 *)
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(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:106" *)
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LUT4 #(
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.INIT(16'h5150)
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) _2_ (
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.A(clr),
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.B(clk),
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.C(pre),
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.D(b2),
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.Z(_0_)
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);
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(* module_not_derived = 32'd1 *)
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(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:108" *)
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LUT4 #(
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.INIT(16'h5554)
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) _3_ (
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.A(clr),
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.B(clk),
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.C(pre),
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.D(b2),
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.Z(_1_)
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);
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(* module_not_derived = 32'd1 *)
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(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:110" *)
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PFUMX _4_ (
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.ALUT(_1_),
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.BLUT(_0_),
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.C0(a),
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.Z(b2)
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);
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(* module_not_derived = 32'd1 *)
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(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *)
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LUT4 #(
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.INIT(16'bx1x1x1x0x0x1x0x0)
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) _5_ (
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.A(1'h0),
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.B(clk),
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.C(b),
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.D(a),
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.Z(b)
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);
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(* module_not_derived = 32'd1 *)
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(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *)
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LUT4 #(
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.INIT(16'bx1x1x0x1x1x0x0x0)
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) _6_ (
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.A(1'h0),
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.B(clk),
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.C(b1),
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.D(a),
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.Z(b1)
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);
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assign \u_latchn.d = a;
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assign \u_latchn.en = clk;
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assign \u_latchn.q = b1;
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assign \u_latchp.d = a;
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assign \u_latchp.en = clk;
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assign \u_latchp.q = b;
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assign \u_latchsr.clr = clr;
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assign \u_latchsr.d = a;
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assign \u_latchsr.en = clk;
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assign \u_latchsr.pre = pre;
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assign \u_latchsr.q = b2;
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endmodule
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