3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-30 04:28:55 +00:00
yosys/techlibs/anlogic
Catherine a727e7f6e7 Migrate build system to CMake
See #5895 for details.

This commit does not include CI or documentation changes.
2026-06-03 08:58:10 +00:00
..
anlogic_eqn.cc
anlogic_fixcarry.cc Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
arith_map.v
brams.txt anlogic: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_map.v anlogic: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
cells_map.v
cells_sim.v
CMakeLists.txt Migrate build system to CMake 2026-06-03 08:58:10 +00:00
eagle_bb.v
lutrams.txt anlogic: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
lutrams_map.v anlogic: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
synth_anlogic.cc Add check before flatten in synth_*. 2026-05-05 14:06:58 +02:00