mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-27 14:37:55 +00:00
4 lines
99 B
Verilog
4 lines
99 B
Verilog
module test(input in, input clk, output reg out);
|
|
always @(posedge clk)
|
|
out <= in;
|
|
endmodule
|