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Code Activity
yosys/techlibs/common
History
Marcelina Kościelnicka 19720b970d memory: Introduce $meminit_v2 cell, with EN input.
2021-07-28 23:18:38 +02:00
..
.gitignore
abc9_map.v techmap: Add support for [] wildcards in techmap_celltype. 2020-08-02 22:46:48 +02:00
abc9_model.v abc9: fix SCC issues (#2694) 2021-03-29 22:01:57 -07:00
abc9_unmap.v abc9: fix SCC issues (#2694) 2021-03-29 22:01:57 -07:00
adff2dff.v Fix syntax error in adff2dff.v 2021-02-24 01:07:34 +01:00
cellhelp.py
cells.lib
cmp2lcu.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
cmp2lut.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
dff2ff.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
gate2lut.v
gen_fine_ffs.py simcells: Fix reset polarity for $_DLATCH_???_ cells. 2020-06-30 15:32:06 +02:00
Makefile.inc
mul2dsp.v Fix files with CRLF line endings 2021-06-09 12:16:33 +02:00
pmux2mux.v
prep.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
simcells.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
simlib.v memory: Introduce $meminit_v2 cell, with EN input. 2021-07-28 23:18:38 +02:00
synth.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
techmap.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00