mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 22:23:23 +00:00
Code Activity
yosys/techlibs/intel_alm/common
History
Lofty 8cc9aa7fc6 intel_alm: drop quartus support
2024-05-03 11:32:33 +01:00
..
abc9_map.v intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY 2020-07-04 19:45:10 +02:00
abc9_model.v intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF 2020-07-04 19:45:10 +02:00
abc9_unmap.v intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY 2020-07-04 19:45:10 +02:00
alm_map.v
alm_sim.v intel_alm: drop quartus support 2024-05-03 11:32:33 +01:00
arith_alm_map.v intel_alm: Fix illegal carry chains 2021-05-15 22:37:06 +01:00
bram_m10k.txt intel_alm: re-enable 8x40-bit M10K support 2023-05-29 06:42:03 +01:00
bram_m10k_map.v intel_alm: re-enable 8x40-bit M10K support 2023-05-29 06:42:03 +01:00
dff_map.v synth_intel_alm: Use dfflegalize. 2020-07-04 22:56:16 +02:00
dff_sim.v intel_alm: drop quartus support 2024-05-03 11:32:33 +01:00
dsp_map.v intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00
dsp_sim.v intel_alm: preliminary Arria V support 2021-11-25 17:20:36 +01:00
lutram_mlab.txt
megafunction_bb.v CycloneV: Add (passthrough) support for cyclonev_oscillator 2021-10-17 20:00:03 +02:00
mem_sim.v intel_alm: drop quartus support 2024-05-03 11:32:33 +01:00
misc_sim.v intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00