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1070f2e90b
Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail.
10 lines
397 B
Plaintext
10 lines
397 B
Plaintext
read_verilog mul.v
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hierarchy -top top
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equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 17 t:EFX_ADD
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select -assert-count 149 t:EFX_LUT4
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select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D
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