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1070f2e90b
Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail.
12 lines
99 B
Verilog
12 lines
99 B
Verilog
module top
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(
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input [7:0] x,
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input [7:0] y,
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output [15:0] A,
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);
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assign A = x * y;
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endmodule
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