mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-11 11:43:38 +00:00
1070f2e90b
Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail.
22 lines
299 B
Verilog
22 lines
299 B
Verilog
module top
|
|
(
|
|
input [7:0] data_a,
|
|
input [8:1] addr_a,
|
|
input we_a, clk,
|
|
output reg [7:0] q_a
|
|
);
|
|
// Declare the RAM variable
|
|
reg [7:0] ram[63:0];
|
|
|
|
// Port A
|
|
always @ (posedge clk)
|
|
begin
|
|
if (we_a)
|
|
begin
|
|
ram[addr_a] <= data_a;
|
|
q_a <= data_a;
|
|
end
|
|
q_a <= ram[addr_a];
|
|
end
|
|
endmodule
|