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1070f2e90b
Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail.
21 lines
606 B
Plaintext
21 lines
606 B
Plaintext
read_verilog latches.v
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design -save read
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proc
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async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
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flatten
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synth_efinix
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equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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design -load read
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synth_efinix
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flatten
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cd top
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#Internall cell type $_DLATCH_P_. Should be realized by using LUTs.
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#The same result by using just synth_efinix.
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select -assert-count 3 t:$_DLATCH_P_
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select -assert-count 3 t:EFX_LUT4
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select -assert-none t:$_DLATCH_P_ t:EFX_LUT4 %% t:* %D
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