mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity
yosys/kernel
History
Ruben Undheim c50afc4246 Documentation improvements etc. 
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
2018-10-13 20:34:44 +02:00
..
bitpattern.h Removed unnecessary cast. 2015-09-01 12:40:36 +02:00
calc.cc Fix mingw compile issue (2nd attempt) 2017-02-23 14:21:02 +01:00
cellaigs.cc Add $_ANDNOT_ and $_ORNOT_ gates 2017-05-17 09:08:29 +02:00
cellaigs.h Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
celledges.cc Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell() 2016-07-25 16:39:25 +02:00
celledges.h Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
celltypes.h Fix IdString M in setup_stdcells() 2018-10-04 15:36:26 +01:00
consteval.h Add ConstEval defaultval feature 2017-04-05 11:25:22 +02:00
cost.h Use quote includes for yosys.h 2017-12-13 13:27:52 -08:00
driver.cc Modify emscripten main to mount nodefs and to run arg as a script 2018-05-18 22:53:52 -07:00
hashlib.h Add hashlib support for hashing of pools 2017-08-22 13:04:33 +02:00
log.cc Provide source-location logging. 2018-07-19 10:22:02 -07:00
log.h Provide source-location logging. 2018-07-19 10:22:02 -07:00
macc.h Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00
modtools.h Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
register.cc Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
register.h Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
rtlil.cc Documentation improvements etc. 2018-10-13 20:34:44 +02:00
rtlil.h Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
satgen.h Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
sigtools.h SigMap performance improvement 2016-02-01 10:10:20 +01:00
utils.h Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
yosys.cc Fix Cygwin build and document needed packages 2018-09-19 10:16:53 +02:00
yosys.h Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00