3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-08-09 23:51:08 +00:00
yosys/passes
2026-07-17 23:38:01 +02:00
..
cmds check: check bufnorm too 2026-07-17 23:38:01 +02:00
equiv equiv_miter: don't copy $input_port 2026-07-17 23:33:03 +02:00
fsm Migrate build system to CMake 2026-06-03 08:58:10 +00:00
hierarchy flatten: disable signorm 2026-07-17 23:38:01 +02:00
memory memory_bram: create blackboxes 2026-07-17 23:38:01 +02:00
opt opt_merge: newcelltypes 2026-07-17 23:38:01 +02:00
pmgen pmgen: hold sigmap pointer instead of owning it 2026-07-17 23:38:01 +02:00
proc Merge branch 'main' into nella/latch-toggle 2026-07-08 11:41:08 +02:00
sat signorm: disable passes that use rewrite_sigspecs 2026-07-17 23:33:02 +02:00
techmap Revert "techmap: call hierarchy on map files to determine port directions" 2026-07-17 23:33:02 +02:00
tests End of file fix 2026-06-23 07:23:41 +02:00
CMakeLists.txt Migrate build system to CMake 2026-06-03 08:58:10 +00:00