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Code
Activity
0f4055d4c6
yosys
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passes
History
Clifford Wolf
6e227e3666
Fixed submod for non-primitive cells
2013-12-02 12:53:55 +01:00
..
abc
Tighter integration of ABC build
2013-11-27 09:08:35 +01:00
cmds
Progress on AppNote 011
2013-11-29 16:42:49 +01:00
extract
Automatically run "proc" on extract map files
2013-07-24 20:19:08 +02:00
fsm
Added detection for endless recursion in fsm_detect pass
2013-10-30 00:47:58 +01:00
hierarchy
Remove auto_wire framework (smarter than the verilog standard)
2013-11-24 17:29:11 +01:00
memory
A fix in memory_dff for write ports with static addresses
2013-12-01 14:08:18 +01:00
opt
Cleanups and bugfixes in response to new internal cell checker
2013-11-11 00:39:45 +01:00
proc
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
sat
Started implementing undef support in "sat" command
2013-11-25 21:40:00 +01:00
scc
fixed typos
2013-03-18 07:28:31 +01:00
submod
Fixed submod for non-primitive cells
2013-12-02 12:53:55 +01:00
techmap
Using simplemap mappers from techmap
2013-11-24 23:31:14 +01:00