mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-20 14:20:32 +00:00
41 lines
No EOL
1.5 KiB
Text
41 lines
No EOL
1.5 KiB
Text
# ISC License
|
|
#
|
|
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
|
|
#
|
|
# Permission to use, copy, modify, and/or distribute this software for any
|
|
# purpose with or without fee is hereby granted, provided that the above
|
|
# copyright notice and this permission notice appear in all copies.
|
|
#
|
|
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
|
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
|
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
|
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
|
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
|
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
|
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
|
|
|
read_verilog <<EOT
|
|
module widemux(
|
|
input [3:0] data,
|
|
input S0,
|
|
input S1,
|
|
output Y
|
|
);
|
|
assign Y = S1 ? (S0 ? data[3] : data[1]) : (S0 ? data[2] : data[0]);
|
|
endmodule
|
|
EOT
|
|
synth_microchip -top widemux -family polarfire -noiopad
|
|
select -assert-count 1 t:MX4
|
|
select -assert-none t:MX4 %% t:* %D
|
|
|
|
# RTL style is different here forming a different structure
|
|
read_verilog ../common/mux.v
|
|
design -save read
|
|
|
|
hierarchy -top mux4
|
|
proc
|
|
equiv_opt -assert -map +/microchip/cells_sim.v synth_microchip -top mux4 -family polarfire -noiopad
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd mux4 # Constrain all select calls below inside the top module
|
|
select -assert-count 3 t:CFG3
|
|
select -assert-none t:CFG3 %% t:* %D |