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0e1661f84e
yosys
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techlibs
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common
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Clifford Wolf
404b46674b
Fixed techmap of $reduce_xnor with multi-bit outputs
2013-11-07 00:58:06 +01:00
..
blackbox.sed
Moved common techlib files to techlibs/common
2013-09-15 11:52:57 +02:00
Makefile.inc
Moved common techlib files to techlibs/common
2013-09-15 11:52:57 +02:00
simlib.v
Added $sr, $dffsr and $dlatch cell types
2013-10-18 11:56:16 +02:00
stdcells.v
Fixed techmap of $reduce_xnor with multi-bit outputs
2013-11-07 00:58:06 +01:00
stdcells_sim.v
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
2013-10-18 12:13:34 +02:00