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111 lines
3.6 KiB
Verilog
111 lines
3.6 KiB
Verilog
// The MLAB
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// --------
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// In addition to Logic Array Blocks (LABs) that contain ten Adaptive Logic
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// Modules (ALMs, see alm_sim.v), the Cyclone V also contains
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// Memory/Logic Array Blocks (MLABs) that can act as either ten ALMs, or utilise
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// the memory the ALM uses to store the look-up table data for general usage,
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// producing a 32 address by 20-bit block of memory. MLABs are spread out
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// around the chip, so they can be placed near where they are needed, rather than
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// being comparatively limited in placement for a deep but narrow memory such as
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// the M10K memory block.
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//
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// MLABs are used mainly for shallow but wide memories, such as CPU register
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// files (which have perhaps 32 registers that are comparatively wide (16/32-bit))
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// or shift registers (by using the output of the Nth bit as input for the N+1th
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// bit).
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//
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// For historical reasons a MISTRAL_MLAB cell represents a 32 address by 1-bit cell,
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// and 20 of them represent a physical MLAB.
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//
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// How the MLAB works
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// ------------------
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// MLABs are poorly documented, so the following information is based mainly
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// on the simulation model and my knowledge of how memories like these work.
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// Additionally, note that the ports of MISTRAL_MLAB are the ones auto-generated
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// by the Yosys `memory_bram` pass, and it doesn't make sense to me to use
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// `techmap` just for the sake of renaming the cell ports.
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//
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// The MLAB can be initialised to any value.
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//
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// The MLAB takes in data from A1DATA at the rising edge of CLK1, and if A1EN
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// is high, writes it to the address in A1ADDR. A1EN can therefore be used to
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// conditionally write data to the MLAB.
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//
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// Simultaneously, the MLAB reads data from B1ADDR, and outputs it to B1DATA,
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// asynchronous to CLK1 and ignoring A1EN. If a synchronous read is needed
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// then the output can be fed to embedded flops.
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// The vendor sim model outputs 'x for a very short period (a few
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// combinational delta cycles) after each write. This has been omitted from
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// the following model because it's very difficult to trigger this in practice
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// as clock cycles will be much longer than any potential blip of 'x, so the
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// model can be treated as always returning a defined result.
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(* abc9_box, lib_whitebox *)
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module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN,
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(* clkbuf_sink *) input CLK1,
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input [4:0] B1ADDR, output B1DATA);
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reg [31:0] mem = 32'b0;
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`ifdef cyclonev
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specify
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$setup(A1ADDR, posedge CLK1, 86);
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$setup(A1DATA, posedge CLK1, 86);
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$setup(A1EN, posedge CLK1, 86);
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(B1ADDR[0] => B1DATA) = 487;
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(B1ADDR[1] => B1DATA) = 475;
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(B1ADDR[2] => B1DATA) = 382;
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(B1ADDR[3] => B1DATA) = 284;
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(B1ADDR[4] => B1DATA) = 96;
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endspecify
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`endif
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always @(posedge CLK1)
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if (A1EN) mem[A1ADDR] <= A1DATA;
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assign B1DATA = mem[B1ADDR];
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endmodule
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// The M10K
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// --------
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// TODO
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module MISTRAL_M10K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter INIT = 0;
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parameter CFG_ABITS = 10;
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parameter CFG_DBITS = 10;
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(* clkbuf_sink *) input CLK1;
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input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
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input [CFG_DBITS-1:0] A1DATA;
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input A1EN, B1EN;
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output reg [CFG_DBITS-1:0] B1DATA;
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reg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = INIT;
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`ifdef cyclonev
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specify
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$setup(A1ADDR, posedge CLK1, 125);
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$setup(A1DATA, posedge CLK1, 97);
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$setup(A1EN, posedge CLK1, 140);
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$setup(B1ADDR, posedge CLK1, 125);
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$setup(B1EN, posedge CLK1, 161);
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if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 1004;
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endspecify
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`endif
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always @(posedge CLK1) begin
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if (!A1EN)
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mem[(A1ADDR + 1) * CFG_DBITS - 1 : A1ADDR * CFG_DBITS] <= A1DATA;
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if (B1EN)
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B1DATA <= mem[(B1ADDR + 1) * CFG_DBITS - 1 : B1ADDR * CFG_DBITS];
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end
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endmodule
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