mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
432 lines
10 KiB
Text
432 lines
10 KiB
Text
pattern ice40_dsp
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state <SigBit> clock
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state <bool> clock_pol cd_signed o_lo
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state <SigSpec> sigA sigB sigCD sigH sigO
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state <Cell*> add mux
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state <IdString> addAB muxAB
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state <Cell*> ffA ffB ffCD
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state <Cell*> ffFJKG ffH ffO
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// subpattern
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state <bool> argSdff
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state <SigSpec> argQ argD
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff
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udata <bool> dffclock_pol
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match mul
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select mul->type.in($mul, \SB_MAC16)
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select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
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endmatch
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code sigA sigB sigH
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auto unextend_signed = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove sign bit
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++i;
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return sig.extract(0, i);
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};
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auto unextend_unsigned = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != SigBit(State::S0))
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break;
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++i;
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return sig.extract(0, i);
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};
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sigA = param(mul, \A_SIGNED).as_bool() ? unextend_signed(port(mul, \A)) : unextend_unsigned(port(mul, \A));
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sigB = param(mul, \B_SIGNED).as_bool() ? unextend_signed(port(mul, \B)) : unextend_unsigned(port(mul, \B));
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SigSpec O;
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if (mul->type == $mul)
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O = mul->getPort(\Y);
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else if (mul->type == \SB_MAC16)
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O = mul->getPort(\O);
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else log_abort();
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if (GetSize(O) <= 10)
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reject;
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// Only care about those bits that are used
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int i;
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for (i = GetSize(O) - 1; i > 0 && nusers(O[i]) <= 1; i--)
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;
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// This sigM could have no users if downstream sinks (e.g. $add) is
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// narrower than $mul result, for example
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if (i == 0)
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reject;
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for (int j = 0, wire_width = 0; j <= i; j++)
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if (nusers(O[j]) == 0)
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wire_width++;
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else {
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if (wire_width) { // add empty wires for bit offset if needed
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sigH.append(module->addWire(NEW_ID, wire_width));
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wire_width = 0;
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}
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sigH.append(O[j]);
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}
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endcode
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code argQ ffA sigA clock clock_pol
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if (mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()) {
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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ffA = dff;
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clock = dffclock;
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clock_pol = dffclock_pol;
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sigA = dffD;
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}
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}
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endcode
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code argQ ffB sigB clock clock_pol
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if (mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()) {
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argQ = sigB;
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subpattern(in_dffe);
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if (dff) {
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ffB = dff;
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clock = dffclock;
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clock_pol = dffclock_pol;
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sigB = dffD;
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}
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}
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endcode
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code argD argSdff ffFJKG sigH clock clock_pol
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if (nusers(sigH) == 2 &&
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(mul->type != \SB_MAC16 ||
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(!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool()))) {
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argD = sigH;
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argSdff = false;
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subpattern(out_dffe);
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if (dff) {
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// F/J/K/G do not have a CE-like (hold) input
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if (dff->hasPort(\EN))
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goto reject_ffFJKG;
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// Reset signal of F/J (IRSTTOP) and K/G (IRSTBOT)
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// shared with A and B
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if (ffA) {
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if (ffA->hasPort(\ARST) != dff->hasPort(\ARST))
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goto reject_ffFJKG;
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if (ffA->hasPort(\ARST)) {
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if (port(ffA, \ARST) != port(dff, \ARST))
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goto reject_ffFJKG;
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if (param(ffA, \ARST_POLARITY) != param(dff, \ARST_POLARITY))
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goto reject_ffFJKG;
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}
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}
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if (ffB) {
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if (ffB->hasPort(\ARST) != dff->hasPort(\ARST))
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goto reject_ffFJKG;
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if (ffB->hasPort(\ARST)) {
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if (port(ffB, \ARST) != port(dff, \ARST))
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goto reject_ffFJKG;
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if (param(ffB, \ARST_POLARITY) != param(dff, \ARST_POLARITY))
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goto reject_ffFJKG;
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}
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}
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ffFJKG = dff;
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clock = dffclock;
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clock_pol = dffclock_pol;
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sigH = dffQ;
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reject_ffFJKG: ;
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}
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}
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endcode
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code argD argSdff ffH sigH sigO clock clock_pol
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if (ffFJKG && nusers(sigH) == 2 &&
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(mul->type != \SB_MAC16 || !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())) {
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argD = sigH;
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argSdff = false;
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subpattern(out_dffe);
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if (dff) {
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// H does not have a CE-like (hold) input
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if (dff->hasPort(\EN))
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goto reject_ffH;
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// Reset signal of H (IRSTBOT) shared with B
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if (ffB->hasPort(\ARST) != dff->hasPort(\ARST))
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goto reject_ffH;
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if (ffB->hasPort(\ARST)) {
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if (port(ffB, \ARST) != port(dff, \ARST))
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goto reject_ffH;
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if (param(ffB, \ARST_POLARITY) != param(dff, \ARST_POLARITY))
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goto reject_ffH;
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}
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ffH = dff;
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clock = dffclock;
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clock_pol = dffclock_pol;
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sigH = dffQ;
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reject_ffH: ;
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}
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}
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sigO = sigH;
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endcode
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match add
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if mul->type != \SB_MAC16 || (param(mul, \TOPOUTPUT_SELECT).as_int() == 3 && param(mul, \BOTOUTPUT_SELECT).as_int() == 3)
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select add->type.in($add)
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choice <IdString> AB {\A, \B}
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select nusers(port(add, AB)) == 2
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index <SigBit> port(add, AB)[0] === sigH[0]
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filter GetSize(port(add, AB)) <= GetSize(sigH)
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filter port(add, AB) == sigH.extract(0, GetSize(port(add, AB)))
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filter nusers(sigH.extract_end(GetSize(port(add, AB)))) <= 1
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set addAB AB
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optional
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endmatch
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code sigCD sigO cd_signed
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if (add) {
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sigCD = port(add, addAB == \A ? \B : \A);
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cd_signed = param(add, addAB == \A ? \B_SIGNED : \A_SIGNED).as_bool();
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int natural_mul_width = GetSize(sigA) + GetSize(sigB);
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int actual_mul_width = GetSize(sigH);
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int actual_acc_width = GetSize(sigCD);
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if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
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reject;
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// If accumulator, check adder width and signedness
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if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(add, \A_SIGNED).as_bool()))
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reject;
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sigO = port(add, \Y);
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}
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endcode
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match mux
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select mux->type == $mux
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choice <IdString> AB {\A, \B}
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select nusers(port(mux, AB)) == 2
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index <SigSpec> port(mux, AB) === sigO
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set muxAB AB
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optional
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endmatch
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code sigO
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if (mux)
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sigO = port(mux, \Y);
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endcode
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code argD argSdff ffO sigO sigCD clock clock_pol cd_signed o_lo
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if (mul->type != \SB_MAC16 ||
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// Ensure that register is not already used
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((param(mul, \TOPOUTPUT_SELECT).as_int() != 1 && param(mul, \BOTOUTPUT_SELECT).as_int() != 1) &&
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// Ensure that OLOADTOP/OLOADBOT is unused or zero
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(port(mul, \OLOADTOP, State::S0).is_fully_zero() && port(mul, \OLOADBOT, State::S0).is_fully_zero()))) {
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dff = nullptr;
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// First try entire sigO
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if (nusers(sigO) == 2) {
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argD = sigO;
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argSdff = !mux;
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subpattern(out_dffe);
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}
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// Otherwise try just its least significant 16 bits
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if (!dff && GetSize(sigO) > 16) {
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argD = sigO.extract(0, 16);
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if (nusers(argD) == 2) {
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argSdff = !mux;
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subpattern(out_dffe);
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o_lo = dff;
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}
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}
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if (dff) {
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ffO = dff;
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clock = dffclock;
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clock_pol = dffclock_pol;
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sigO.replace(sigO.extract(0, GetSize(dffQ)), dffQ);
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}
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// Loading value into output register is not
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// supported unless using accumulator
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if (mux) {
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if (sigCD != sigO)
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reject;
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sigCD = port(mux, muxAB == \B ? \A : \B);
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cd_signed = add && param(add, \A_SIGNED).as_bool() && param(add, \B_SIGNED).as_bool();
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} else if (dff && dff->hasPort(\SRST)) {
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if (sigCD != sigO)
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reject;
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sigCD = param(dff, \SRST_VALUE);
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cd_signed = add && param(add, \A_SIGNED).as_bool() && param(add, \B_SIGNED).as_bool();
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}
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}
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endcode
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code argQ ffCD sigCD clock clock_pol
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if (!sigCD.empty() && sigCD != sigO &&
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(mul->type != \SB_MAC16 || (!param(mul, \C_REG).as_bool() && !param(mul, \D_REG).as_bool()))) {
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argQ = sigCD;
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subpattern(in_dffe);
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if (dff) {
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// Reset signal of C (IRSTTOP) and D (IRSTBOT)
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// shared with A and B
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if (ffA) {
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if (ffA->hasPort(\ARST) != dff->hasPort(\ARST))
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goto reject_ffCD;
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if (ffA->hasPort(\ARST)) {
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if (port(ffA, \ARST) != port(dff, \ARST))
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goto reject_ffCD;
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if (param(ffA, \ARST_POLARITY) != param(dff, \ARST_POLARITY))
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goto reject_ffCD;
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}
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}
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if (ffB) {
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if (ffB->hasPort(\ARST) != dff->hasPort(\ARST))
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goto reject_ffCD;
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if (ffB->hasPort(\ARST)) {
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if (port(ffB, \ARST) != port(dff, \ARST))
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goto reject_ffCD;
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if (param(ffB, \ARST_POLARITY) != param(dff, \ARST_POLARITY))
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goto reject_ffCD;
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}
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}
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ffCD = dff;
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clock = dffclock;
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clock_pol = dffclock_pol;
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sigCD = dffD;
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reject_ffCD: ;
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}
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}
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endcode
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code sigCD
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sigCD.extend_u0(32, cd_signed);
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endcode
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code
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accept;
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endcode
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// #######################
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subpattern in_dffe
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arg argD argQ clock clock_pol
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code
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dff = nullptr;
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if (argQ.empty())
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reject;
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for (auto c : argQ.chunks()) {
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if (!c.wire)
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reject;
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if (c.wire->get_bool_attribute(\keep))
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reject;
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Const init = c.wire->attributes.at(\init, State::Sx);
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if (!init.is_fully_undef() && !init.is_fully_zero())
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reject;
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}
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endcode
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match ff
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select ff->type.in($dff, $dffe)
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// DSP48E1 does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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slice offset GetSize(port(ff, \D))
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index <SigBit> port(ff, \Q)[offset] === argQ[0]
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// Check that the rest of argQ is present
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filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
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filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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endmatch
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code argQ argD
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{
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if (clock != SigBit()) {
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if (port(ff, \CLK)[0] != clock)
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reject;
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if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
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reject;
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}
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SigSpec Q = port(ff, \Q);
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dff = ff;
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dffclock = port(ff, \CLK);
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dffclock_pol = param(ff, \CLK_POLARITY).as_bool();
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dffD = argQ;
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argD = port(ff, \D);
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argQ = Q;
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dffD.replace(argQ, argD);
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}
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endcode
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// #######################
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subpattern out_dffe
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arg argD argSdff argQ clock clock_pol
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code
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dff = nullptr;
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for (auto c : argD.chunks())
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if (c.wire->get_bool_attribute(\keep))
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reject;
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endcode
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match ff
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select ff->type.in($dff, $dffe, $sdff, $sdffce)
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// SB_MAC16 does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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slice offset GetSize(port(ff, \D))
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index <SigBit> port(ff, \D)[offset] === argD[0]
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// Only allow sync reset if requested.
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filter argSdff || ff->type.in($dff, $dffe)
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// Check that the rest of argD is present
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filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
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filter port(ff, \D).extract(offset, GetSize(argD)) == argD
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endmatch
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code argQ
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if (ff) {
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if (clock != SigBit()) {
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if (port(ff, \CLK)[0] != clock)
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reject;
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if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
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reject;
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}
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SigSpec D = port(ff, \D);
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SigSpec Q = port(ff, \Q);
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argQ = argD;
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argQ.replace(D, Q);
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for (auto c : argQ.chunks()) {
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Const init = c.wire->attributes.at(\init, State::Sx);
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if (!init.is_fully_undef() && !init.is_fully_zero())
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reject;
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}
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dff = ff;
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dffQ = argQ;
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dffclock = port(ff, \CLK);
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dffclock_pol = param(ff, \CLK_POLARITY).as_bool();
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}
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endcode
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