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0d8e5d965f
- Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
23 lines
339 B
Plaintext
23 lines
339 B
Plaintext
read_verilog port_sign_extend.v
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hierarchy
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flatten
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equiv_make ref act equiv
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equiv_simple
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equiv_status -assert
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delete
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read_verilog port_sign_extend.v
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flatten
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equiv_make ref act equiv
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equiv_simple
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equiv_status -assert
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delete
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read_verilog port_sign_extend.v
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hierarchy
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equiv_make ref act equiv
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prep -flatten -top equiv
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equiv_status -assert
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