Zachary Snow 0d8e5d965f Sign extend port connections where necessary ... - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265		2020-12-18 20:33:14 -07:00
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cmds	bugpoint: add -wires option.	2020-12-07 09:24:35 +00:00
equiv	use the new isPublic() in a few places	2020-09-14 12:43:18 +02:00
fsm	Use C++11 final/override keywords.	2020-06-18 23:34:52 +00:00
hierarchy	Sign extend port connections where necessary	2020-12-18 20:33:14 -07:00
memory	memory_dff: Fix needlessly duplicating enable bits.	2020-10-22 13:03:42 +02:00
opt	opt_mem: Use Mem helpers.	2020-10-21 17:51:20 +02:00
pmgen	Return nice error in pmgen generated code, fixes #2482	2020-12-09 11:06:22 +01:00
proc	proc: Add -nomux switch	2020-08-20 22:58:08 +02:00
sat	Add #include needed to build with gcc-11	2020-11-26 06:12:12 -05:00
techmap	Sign extend port connections where necessary	2020-12-18 20:33:14 -07:00
tests	Replace "ILANG" with "RTLIL" everywhere.	2020-08-26 17:29:32 +00:00