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yosys/tests/verilog/bug2042-sv.ys
2020-05-13 10:11:45 -07:00

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read_verilog -sv <<EOT
module Task_Test_Top
(
input a,
output b
);
task SomeTaskName(a);
b = ~a;
endtask
always @*
SomeTaskName(a);
assert property (b == ~a);
endmodule
EOT
proc
sat -verify -prove-asserts
design -reset
logger -expect error "syntax error, unexpected TOK_ENDTASK, expecting ';'" 1
read_verilog -sv <<EOT
module Task_Test_Top
(
);
task SomeTaskName(a)
endtask
endmodule
EOT