Eddie Hung 65c8ccf7b5 Add broken testcases		2019-02-25 15:06:23 -08:00
..
aiger	Support and differentiate between ASCII and binary AIG testing	2019-02-08 12:41:59 -08:00
asicworld	Append (instead of over-writing) EXTRA_FLAGS	2019-02-15 11:56:51 -08:00
bram
errors	Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,	2018-10-25 02:37:56 +03:00
fsm
hana
lut	cmp2lut: new techmap pass.	2019-01-02 07:53:31 +00:00
memories
opt	opt_expr: improve simplification of comparisons with large constants.	2019-01-02 15:45:28 +00:00
realmath
sat	Allow $size and $bits in verilog mode, actually check test case	2017-09-29 11:56:43 +02:00
share
simple	Merge https://github.com/YosysHQ/yosys into dff_init	2019-02-17 11:49:06 -08:00
simple_abc9	Add broken testcases	2019-02-25 15:06:23 -08:00
smv
sva	Squelch a little more trailing whitespace	2018-12-29 12:46:54 +01:00
svinterfaces	Add missing .gitignore	2018-12-06 07:29:37 +01:00
techmap	Move tests/techmap/abc9 to simple_abc9	2019-02-20 15:34:59 -08:00
tools	Revert "tests/simple to also do LUT synth"	2019-02-21 13:15:45 -08:00
unit	Build hotfix in tests/unit/Makefile	2016-12-11 10:58:49 +01:00
various	Modified errors into warnings	2018-06-05 18:03:22 +03:00
vloghtb