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yosys/tests
gatecat 48efc9b75c gatemate: Add test for LUT tree mapping
Signed-off-by: gatecat <gatecat@ds0.me>
2022-06-27 10:09:48 +01:00
..
aiger
arch gatemate: Add test for LUT tree mapping 2022-06-27 10:09:48 +01:00
asicworld
bind
blif Adding expected error message. 2022-06-22 00:34:49 +01:00
bram Fix the tests we just broke 2021-12-10 00:22:37 +01:00
errors
fsm
hana
liberty
lut
memfile
memlib Add memory_libmap tests. 2022-05-18 17:32:56 +02:00
memories Fix the tests we just broke 2021-12-10 00:22:37 +01:00
opt Add memory_bmux2rom pass. 2022-05-18 22:48:55 +02:00
opt_share
proc proc_rom: Add special handling of const-0 address bits. 2022-05-18 17:32:30 +02:00
realmath
rpc
sat Proper example code 2022-03-14 15:39:11 +01:00
select
share
sim test dlatchsr and adlatch 2022-02-16 13:58:51 +01:00
simple Fix valgrind tests when using verific 2022-03-30 17:25:53 +02:00
simple_abc9
smv
sva verific: Use new value change logic also for $stable of wide signals. 2022-05-11 13:05:27 +02:00
svinterfaces
svtypes
techmap opt_mem: Remove constant-value bit lanes. 2022-05-07 23:13:16 +02:00
tools
unit
various smt2: emit smtlib2_comb_expr outputs after all inputs 2022-06-07 19:06:45 +02:00
verilog verilog: fix width/sign detection for functions 2022-05-30 16:45:39 -04:00
vloghtb
gen-tests-makefile.sh