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92 lines
1.3 KiB
Verilog
92 lines
1.3 KiB
Verilog
module nested(
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input clk,
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input [7:0] A,
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input [7:0] B,
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input [3:0] mode1,
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input [3:0] mode2,
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output reg [7:0] result1,
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output reg [7:0] result2,
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output reg [1:0] arith
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);
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localparam OP_A = 4'b0000;
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localparam OP_BA = 4'b0001;
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localparam OP_BB = 4'b0010;
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localparam OP_C = 4'b0011;
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always @(posedge clk)
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begin
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case (mode1)
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OP_A: begin
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result1 = A + B;
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result2 = A - B;
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arith = 2'b01;
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end
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OP_BA , OP_BB : begin
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result1 = A * B;
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result2 = A / B;
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arith = 2'b00;
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end
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OP_C : begin
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arith = 2'b10;
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case (mode2)
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OP_A: begin
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result1 = ~B;
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result2 = B;
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end
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OP_C: begin
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result1 = A ^ B;
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result2 = A == B;
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end
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default: begin
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result1 = 1'b0;
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// result2 omitted
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end
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endcase
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end
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default: begin
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result1 = 8'b0;
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result2 = 8'b0;
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arith = 2'b11;
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end
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endcase
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end
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endmodule
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module tiny(
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input clk,
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input ya,
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input [7:0] in,
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output reg [7:0] out,
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);
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always @(posedge clk)
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begin
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case (ya)
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1'b1: begin
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out = in;
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end
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endcase
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end
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endmodule
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module tiny2(
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input clk,
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input [1:0] ya,
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input [7:0] in,
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output reg [7:0] out,
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);
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always @(posedge clk)
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begin
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case (ya)
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2'b01: begin
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out = in;
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end
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2'b10: begin
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out = 1'b1;
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end
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default begin
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out = 1'b0;
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end
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endcase
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end
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endmodule
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