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40 lines
1.6 KiB
Text
40 lines
1.6 KiB
Text
# Test that proc_mux uses a dominant-value pre-scan to avoid generating
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# unnecessary mux cells when a full_case switch has a majority of arms
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# assigning the same value.
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# 3 of 4 arms assign identical constants for both outputs.
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# The optimization should seed the result with the dominant values (3'b001,
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# 2'b00) so only the one differing arm (2'b00 -> 3'b110, 2'b11) generates
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# cells. Each output word is a separate SigSnippet, so we expect one
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# $logic_not + one $mux per word = 2 of each total.
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read_verilog proc_mux_dominant.v
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hierarchy -top dominant_explicit
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proc
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select -assert-count 2 t:$logic_not
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select -assert-count 2 t:$mux
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select -assert-count 0 t:$eq
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select -assert-count 0 t:$pmux
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# 3 of 4 arms pass through an input wire 'a'. The dominant value is a wire
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# signal rather than a constant; the optimization must still recognise it.
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# Only one arm differs (2'b00 -> 3'b110), producing 1 $logic_not + 1 $mux.
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design -reset
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read_verilog proc_mux_dominant.v
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hierarchy -top dominant_wire
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proc
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select -assert-count 1 t:$logic_not
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select -assert-count 1 t:$mux
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select -assert-count 0 t:$eq
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select -assert-count 0 t:$pmux
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# All four arms assign distinct values; no majority exists. The optimization
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# must not fire and the generated netlist must be functionally correct.
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design -reset
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read_verilog proc_mux_dominant.v
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hierarchy -top no_dominant
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proc
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# Three explicit non-zero compare arms each produce an $eq; the 2'b00 arm
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# uses $logic_not (all-zero check); all results are merged into one $pmux.
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select -assert-count 3 t:$eq
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select -assert-count 1 t:$logic_not
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select -assert-count 1 t:$pmux
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