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331ac5285f
Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions.
38 lines
620 B
Plaintext
38 lines
620 B
Plaintext
logger -expect-no-warnings
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read_verilog -formal <<EOT
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module top(input clk);
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reg signed [3:0] value = -1;
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reg ready = 0;
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always @(posedge clk) begin
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if (ready)
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assert ($past(value) == -1);
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ready <= 1;
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end
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endmodule
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EOT
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prep -top top
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async2sync
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sim -n 3 -clock clk
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design -reset
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read_verilog -formal <<EOT
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module top(input clk);
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reg signed [3:0] value = -1;
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reg ready = 0;
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always @(posedge clk) begin
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if (ready)
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assert ($past(value + 4'b0000) == 15);
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ready <= 1;
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end
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endmodule
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EOT
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prep -top top
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async2sync
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sim -n 3 -clock clk
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