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yosys/tests/verilog/param_no_default.ys
Jannis Harder 0470cbb00d hierarchy: Without a known top module, derive all deferred modules
This fixes hierarchy when used with cell libraries that were loaded with
-defer and also makes more of the hierarchy visible to the auto-top
heuristic.
2024-02-06 10:31:40 +01:00

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read_verilog -sv param_no_default.sv
hierarchy -top top
proc
flatten
opt -full
async2sync
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all