mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
f2c2d73f36
- disallow [gen]blocks with an end label but not begin label - check validity of module end label - fix memory leak of package name and end label - fix memory leak of module end label
16 lines
328 B
Plaintext
16 lines
328 B
Plaintext
logger -expect-no-warnings
|
|
read_verilog -sv <<EOF
|
|
module correct_name;
|
|
localparam X = 1;
|
|
endmodule : correct_name
|
|
EOF
|
|
|
|
design -reset
|
|
|
|
logger -expect error "Module name \(correct_name\) and end label \(incorrect_name\) don't match\." 1
|
|
read_verilog -sv <<EOF
|
|
module correct_name;
|
|
localparam X = 1;
|
|
endmodule : incorrect_name
|
|
EOF
|